Search results for "FPGA prototype"
showing 7 items of 7 documents
Multiprocessor SoC Implementation of Neural Network Training on FPGA
2008
Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…
Hardware implementation of a robust adaptive filter: Two approaches based in High-Level Synthesis design tools
2009
Abstract Adaptive filters are used in a wide range of applications. Impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms. Field Programmable Gate Array (FPGA) are widely used for applications where timing requirements are strict. Nowadays, two main design processes can be followed, namely, Hardware Description Language (HDL) and a High Level Synthesis (HLS) design tool for embedded system design. This paper describes the FPGA implementation of an adaptive filter robust to impulsive noise using two approaches based in HLS and the implementati…
Communication Interface Generation For HW/SW Architecture In The STARSoC Environment
2006
Mapping the application functionality to software and hardware requires automated methods to specify, generate and optimize the hardware, software, and the interface architectures between them. In this paper, we present a methodology flow to hardware-software communication synthesis for system-on-a-chip (SoC) design through STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-on-a-Chip) tool for rapid prototyping. Our concept consists of a set of hardware and software processes, described in C-code, communicates through the streams channels. This methodology consists in analyzing dependences of data between processes and synthesis a custom architecture to interface it. Firstly, we…
Flexible VLIW processor based on FPGA for real-time image processing
2011
Modern FPGA chips, with their larger memory capacity and reconfigurability potential, are opening new frontiers in rapid prototyping of embedded systems. With the advent of high density FPGAs it is now possible to implement a high performance Very Long Instruction Word (VLIW) processor core in an FPGA. With VLIW architecture, the processor effectiveness depends on the ability of compilers to provide sufficient Instruction Level Parallelism (ILP) from program code. This paper describes research result about enabling the VLIW processor model for real-time processing applications by exploiting FPGA technology. Our goals are to keep the flexibility of processors in order to shorten the developm…
A Sliced Coprocessor for Native Clifford Algebra Operations
2007
Computer graphics applications require efficient tools to model geometric objects. The traditional approach based on compute-intensive matrix calculations is error-prone due to a lack of integration between geometric reasoning and matrix-based algorithms. Clifford algebra offers a solution to these issues since it permits specification of geometry at a coordinate-free level. The best way to exploit the symbolic computing power of geometric (Clifford) algebra is supporting its data types and operators directly in hardware. This paper outlines the architecture of S-CliffoSor (Sliced Clifford coprocessor), a parallelizable embedded coprocessor that executes native Clifford algebra operations. …
A Dual-Core Coprocessor with Native 4D Clifford Algebra Support
2012
Geometric or Clifford Algebra (CA) is a powerful mathematical tool that is attracting a growing attention in many research fields such as computer graphics, computer vision, robotics and medical imaging for its natural and intuitive way to represent geometric objects and their transformations. This paper introduces the architecture of CliffordCoreDuo, an embedded dual-core coprocessor that offers direct hardware support to four-dimensional (4D) Clifford algebra operations. A prototype implementation on an FPGA board is detailed. Experimental results show a 1.6× average speedup of CliffordCoreDuo in comparison with the baseline mono-core architecture. A potential cycle speedup of about 40× o…
A hardware skin-segmentation IP for vision based smart ADAS through an FPGA prototyping
2017
International audience; In this paper we presents a platform based design approach for fast HW/SW embedded smart Advanced Driver Assistant System (ADAS) design and prototyping. Then, we share our experience in designing and prototyping a HW/SW vision based smart embedded system as an ADAS that helps to increase the safety of car's drivers. We present a physical prototype of the vision ADAS based on a Zynq FPGA. The system detects the fatigue state of the driver by monitoring the eyes closure and generates a real-time alert. A new HW/SW codesign skin segmentation step to locate the eyes/face is proposed. Our presented new approach migrates the skin segmentation step from processing system (S…